INTELLECTUAL POWER AWARE ROUTING(IPAR) METHODOLOGY FOR CONFIGURING NOC ARCHITECTURE

Abstract

Recently, System On Chip finds its applications in the hard-real time fields like Medical, Tele-Emergency, Automotives, Hospital management systems. These areas require more attention in terms of power and intelligence. To meet this above criterion, System on Chip Architecture itself needs the redefinition in terms of Core Interconnection architectures. Nowadays Implementation of Network On Chip(NoC) is popular for SoC but meeting the Power efficiency and intelligence in NOC routing is a strained challenge among the researchers. Hence we propose the new algorithm called Intellectual Power-Aware Routing(IPAR) for making the NoC flexible and scalable for the SoC architectures which can be further implemented for the Hard-Real Time Applications.