APPLICATION OF UT MULTIPLIER IN AES ALGORITHM AND ANALYSIS OF ITS PERFORMANCE

Abstract

From the previous few years numerous cryptographic algorithms have been implemented, giving scrupulous significance to high safety applications, i.e. for ATMs, smart cards, WWW servers & many others. Amid the specified cryptographic algorithms, the Advanced Encryption Standard (AES) algorithm is preferred algorithm. The algorithm is implemented in various bit sizes. An AES algorithm recognizes a 128-bit plain data text and generates a 128-bit cipher text under the secret key control of 128, 192 or 256-bits. Moreover in this brief, an AES algorithm with 128/192/256 bits is implemented by using Vedic Mathematics. The conventional pipelined based algorithm is compared with proposed Vedic mathematics based AES algorithm in turns of area. With the help of Xilinx the AES algorithm is simulated and synthesized. Also it can be seen that proposed algorithm occupies approximately 40% less area when compared with conventional algorithm.