HDL Implementation of Scalable Architecture for Packet Classification using Field Split Bit Vector Algorithm

Abstract

The categorization of incoming packets can be considered as a classification based on the fields of the different headers, such as the source-Internet protocol, the target-Internet protocol, the source-port, destination-port and protocol fields. It requires that each packet is compared with rules and each packet is forwarded to the highest priority matching rule. Packet classification performance also depends on the rule sets. The required storage depends generally on the number of rules and the size of the method. In this paper, we described a Modular Field Split Bit-Vector (FSBV) algorithm, with which the Field Programmable Gate Array (FPGA) classification of packets is performed using Xilinx ISE13.1 software, with a few predefined rules. From the results obtained through EDA tools, it can be concluded that the proposed technique is memory-efficient and latency aware.